utc 3511 cmos ic utc unisonic technologies co., ltd. 1 qw-r502-015,b pc power supply supervisors description the utc 3511 provides protection circuits, power good output (pgo), fault protection latch (fpl_n), and protection detector function (pdon_n) control. it can minimize external components of switching power supply systems in personal computer. the over voltage detector (ovd) monitors 3.3v, 5v, 12v input voltage level. the under voltage detector (uvd) monitors 3.3v, 5v input voltage level. when ovd or uvd detect the fault voltage level, the fpl_n is latched high and pgo goes low. the latch can be reset by pdon_n going high. there is 2.4ms delay time for pdon_n turning off fpl_n. when ovd and uvd detect the right voltage level, the power good output (pgo) will be issue. features * the over voltage detector (ovd) monitors 3.3v, 5v, 12v input voltage level. * the under voltage detector (uvd) monitors 3.3v, 5v input voltage level. * both of the power good output (pgo) and the fault protection latch (fpl_n) are open drain output. * 75 ms time delay for uvd. * 300 ms time delay for pgo. * 38 ms for pdon_n input signal de-bounce. * 73 us for internal signal de-glitches. * 2.4 ms time delay for pdon_n turn-off fpl_n. dip-8 sop-8 pin configuration pgi gnd fpl_n pdon_n v33 v5 vdd pgo 1 2 3 4 8 7 6 5
utc 3511 cmos ic utc unisonic technologies co., ltd. 2 qw-r502-015,b pin description pin no. pin name type description 1 pgi i power good input pin 2 gnd p ground 3 fpl-n o fault protection latch output pin (open drain output) 4 pdon-n i protection detector function on/off control input pin 5 v33 i 3.3v input pin 6 v5 i 5v input pin 7 vdd i supply voltage/12v input pin 8 pgo o power good output pin(open drain output) block diagram pdon_n v dd 150ua 3.6v power on reset vcc low voltage por lvrst clock generator clk pwr v33 v5 v dd pgi 1.2v un - + - + - + - + - + - + clk rst 73us debounce clk clr 300ms delay v dd pgo fpl_n r s q clk rst 73us debounce clr 75ms delay clk rwr clk pwr 38ms debounce rst clk pwr 2.4ms delay clr ov ov un ov un absolute maximum ratings parameter symbol ratings unit supply voltage v dd -0.3 ~ 16 v input voltage pdon_n,v5,v33,pgi vin -0.3 ~ 7 v -0.3 ~ 16 output voltage fpl_n pgo v out -0.3 ~ 7 v operating temperature topr -40 ~ 125 c storage temperature tstg -55 ~ 150 c note:stresses above those listed may cause permanent damage to the devices
utc 3511 cmos ic utc unisonic technologies co., ltd. 3 qw-r502-015,b recommended operating conditions parameter symbol min typ max unit supply voltage v dd 3.8 12 15 v input voltage pdon_n,v5,v33,pgi vin 7 v 15 v output voltage fpl_n pgo v out 7 v 30 ma output sink current fpl_n pgo iosink 10 ma supply voltage rising time trs 1 ms electrical characteristics (ta=25 , v dd =5v) over voltage detection parameter symbol test conditions min typ. max unit v33 3.7 3.9 4.1 v5 5.7 6.1 6.5 over voltage threshold v dd / v12 12.8 13.4 13.9 v leakage current (fpl_n) i leakage fpl_n=5v 5 ua i sink =10ma 0.3 low level output voltage (fpl_n) v ol i sink =30ma 0.7 v pgi and pgo parameter symbol test conditions min typ. max unit v33 2.55 2.69 2.83 under voltage threshold v5 4.1 4.3 4.47 input threshold voltage (pgi) v pgi 1.16 1.20 1.24 v leakage current (pgo) i leakage pgo=5v 5 ua low level output voltage (pgo) v ol i sink =10ma 0.4 v pdon_n parameter symbol test conditions min typ. max unit input pull-up current i l pdon_n=0v 150 ua high-level input voltage v ih 2.4 v low-level input voltage v il 1.2 v total device parameter symbol test conditions min typ. max unit supply current icc pdon_n=5v 1 ma low voltage v dd 3 v
utc 3511 cmos ic utc unisonic technologies co., ltd. 4 qw-r502-015,b switching characteristics, v dd =5v parameter symbol test conditions min typ. max unit de-bounce time (pdon_n) t db1 32 38 61 ms delay time (pgi to pgo) t delay ta=-40 c ~ 125 c 200 300 490 ms de-bounce time (pdon_n) t db2 32 38 61 ms de-glitch time t g 63 73 120 us pdon_n to fpl_n delay time t delay2 t db2 +2.0 t db2 +2.4 t db2 +3.8 ms internal uvd delay time t delay3 fpl_n go low & every time pgi>1.2v 65 75 122 ms application circuit 5v pgi 470 pdon_n 0.01uf 1 2 3 4 8 7 6 5 0.01uf 5v 12v vsb pgi gnd fpl_n pdon_n pgo vdd v5 v33 3511 3.3v 5v
utc 3511 cmos ic utc unisonic technologies co., ltd. 5 qw-r502-015,b application timming 1. pgi (under_voltage): pdon_n fpl_n pgo pgi t db1 t delay1+ t g t delay2 t db2 t delay1+ t g pdon_n fpl_n pgo pgi t db1 t delay1+ t g t delay2 t db2
utc 3511 cmos ic utc unisonic technologies co., ltd. 6 qw-r502-015,b 2. v33,v5 (under_voltage): pdon_n fpl_n pgo pgi t db1 t delay3+ t g t delay2 t db2 t delay1+ t g v33 / v5 t db1 t delay3 =75ms pdon_n fpl_n pgo v33 / v5 t db1 t delay1+ t g t delay2 t db2
utc 3511 cmos ic utc unisonic technologies co., ltd. 7 qw-r502-015,b 3. v33,v5,v12 (over_voltage): pdon_n fpl_n pgo t db1 t delay2 t db2 t delay1+ t g v33 / v5 / v12 t g t db1 pdon_n fpl_n pgo t db1 t delay1+ t g t delay2 t db2 v33 / v5 / v12 utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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